I am a PhD student in Electrical Engineering at Stanford University, advised by Professor
Sara Achour
and Professor Mark Horowitz.
I build domain-specific compilers for quantum computing, quantum simulation and
sparse tensor algebra. My interests more broadly span
compilers, computer architecture and hardware modeling.
During my PhD, I have interned twice at Google. In Summer 2026, I developed a scheduling language and an agent-based auto-scheduling framework for the Darwinn Edge-TPU compiler. In Summer 2025, I worked with the ODML team on KV-cache pruning techniques for infinite-context large language model inference on edge devices, in LiteRT-LM.
Earlier, in Summer 2022, I was a research intern at IonQ, building efficient near-term error-correction implementations for Bacon-Shor codes.
I graduated from the Indian Institute of Technology (IIT) Delhi in 2021 with a degree
in Electrical Engineering. At IIT Delhi, I was
fortunate to be advised by Professor Debanjan Bhowmik and worked
with Professor Gert Cauwenberghs at UCSD and Professor Niraj Jha
at Princeton University on compute-in-memory hardware accelerators.
News
Publications
CoTenN: Constrained Optimization with Tensor Networks
Ritvik Sharma,
Cheng Peng,
Siddharth Dangwal,
and
Sara Achour
Conference on Programming Language Design and Implementation (PLDI), Volume 10, Issue PLDI, June 2026
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FuseFlow: A Fusion-Centric Compilation Framework for Sparse Deep Learning on Streaming Dataflow
Rubens Lacouture,
Nathan Zhang,
Ritvik Sharma,
Marco Siracusa,
Fredrik Kjolstad,
Kunle Olukotun,
and
Olivia Hsu
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Volume 2, March 2026
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A Probabilistic Perspective on Tiling Sparse Tensor Algebra
Ritvik Sharma,
Zi Yu Xue,
Nathan Zhang,
Rubens Lacouture,
Fredrik Kjolstad,
Sara Achour,
and
Mark Horowitz
IEEE/ACM International Symposium on Microarchitecture (MICRO), November 2025
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Optimizing Ancilla-Based Quantum Circuits with SPARE
Ritvik Sharma
and
Sara Achour
Conference on Programming Language Design and Implementation (PLDI), June 2025
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Compilation of Qubit Circuits to Optimized Qutrit Circuits
Ritvik Sharma
and
Sara Achour
Conference on Programming Language Design and Implementation (PLDI), June 2024
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Onyx: A Programmable Accelerator for Sparse Tensor Algebra
Kalhan Koul,
Maxwell Strange,
Jackson Melchert,
Alex Carsello,
Yuchen Mei,
Olivia Hsu,
Taeyoung Kong,
Po-Han Chen,
Jake Ke,
Keyi Zhang,
Qiaoyi Liu,
Gedeon Nyengele,
Akhilesh Balasingam,
Jayashree Adivarahan,
Ritvik Sharma,
Zhouhua Xie,
Christopher Torng,
Joel Emer,
Fredrik Kjolstad,
Mark Horowitz,
and
Priyanka Raina
IEEE Hot Chips Symposium (Hot Chips), August 2024
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Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications
Kalhan Koul,
Maxwell Strange,
Jackson Melchert,
Alex Carsello,
Yuchen Mei,
Olivia Hsu,
Taeyoung Kong,
Po-Han Chen,
Jake Ke,
Keyi Zhang,
Qiaoyi Liu,
Gedeon Nyengele,
Akhilesh Balasingam,
Jayashree Adivarahan,
Ritvik Sharma,
Zhouhua Xie,
Christopher Torng,
Joel Emer,
Fredrik Kjolstad,
Mark Horowitz,
and
Priyanka Raina
IEEE Symposium on VLSI Technology & Circuits (VLSI), June 2024
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The Sparse Abstract Machine
Olivia Hsu,
Maxwell Strange,
Ritvik Sharma,
Jaeyeon Won,
Kunle Olukotun,
Joel Emer,
Mark Horowitz,
and
Fredrik Kjolstad
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2023
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APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis
Jackson Melchert,
Kathleen Feng,
Caleb Donovick,
Ross Daly,
Ritvik Sharma,
Clark Barrett,
Mark Horowitz,
Pat Hanrahan,
and
Priyanka Raina
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2023
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CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework
Shikhar Tuli,
Chia-Hao Li,
Ritvik Sharma,
and
Niraj Jha
ACM Transactions on Embedded Computing Systems (TECS), April 2023
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A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning
Janak Sharda,
Ritvik Sharma,
and
Debanjan Bhowmik
IEEE International Symposium on Circuits and Systems (ISCAS), May 2021
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A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding
Raj Kubendran,
Jongkil Park,
Ritvik Sharma,
Chul Kim,
Siddharth Joshi,
Gert Cauwenberghs,
and
Sohmyung Ha
IEEE International Symposium on Circuits and Systems (ISCAS), May 2020
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Teaching
EE 205: Signals and Systems
Spring 2020-2021, Indian Institute of Technology (IIT), Delhi
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EE 205: Signals and Systems
Fall 2020-2021, Indian Institute of Technology (IIT), Delhi
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